| 摘要 |
In a layout pattern generating method, a specific rework cell used for edition is specified among rework cells and fill cells which are arranged in a semiconductor chip area and a specific pattern of a predetermined shape is generated in a wiring layer for the specific rework cell. A dummy wiring pattern is arranged in at least a part of the wiring layer of and the fill cell and un-specific rework cells among the rework cell other than the specific rework cell. The specific pattern is deleted from the wiring layer for the specifying rework cell. A wiring pattern is arranged in the wiring layer for the specific rework cell by wiring the specific rework cell as a logic cell.
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