发明名称 CLOCK GENERATION CIRCUIT AND INTEGRATED CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To output a plurality of clocks in which a phase relation becomes constant in accordance with the cycle of an external clock, even if there is fluctuations in element characteristics due to power source voltage, variations in the temperature and manufacturing process. <P>SOLUTION: A clock generating circuit includes a first generating part 130 for outputting a first clock delayed by a first delay element 101 to the external clock; a second generating part 140 for outputting a second clock delayed by a second delay element 102; and a control part 120, which uses a plurality of third delay elements 127, each having a delay amount which is correlational with respect to the delay amounts of the first delay element and the second delay elements to control the third delay elements so that the total of delay amounts of the plurality of third delay elements 127 is a target value that depends upon the cycle of the external clock and which uses a control signal to control the delay amount of the first delay element 101, the delay amount of the second delay element 102 and the delay amount of the third delay element 127. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
申请公布号 JP2010128988(A) 申请公布日期 2010.06.10
申请号 JP20080305627 申请日期 2008.11.28
申请人 CANON INC 发明人 YOSHIDA DAISUKE
分类号 G06F1/06;H03K5/00;H03K5/13;H03L7/081 主分类号 G06F1/06
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