REDUCED TOPOGRAPHY-RELATED IRREGULARITIES DURING THE PATTERNING OF TWO DIFFERENT STRESS-INDUCING LAYERS IN THE CONTACT LEVEL OF A SEMICONDUCTOR DEVICE

摘要

In sophisticated semiconductor devices (200), stress-inducing materials (230, 240) may be provided above the basic transistor devices (222) without any etch control or etch stop materials, thereby enabling an efficient de-escalation of the surface topography, in particular above field regions including closely spaced polysilicon lines (222). Furthermore, an additional stress-inducing material (235) may be provided on the basis of the superior surface topography, thereby providing a highly efficient strain-inducing mechanism in performance-driven transistor elements (222P, 222N).