| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a pseudo dual port DRAM which performs dual-port access properly while holding a clock cycle. Ž<P>SOLUTION: The semiconductor storage device includes a plurality of DRAM cells MC, a plurality of sense amplifiers 102 connected to the corresponding bit-line pairs respectively, a first and second column switches 106 and 107 assigned to each of the sense amplifiers 102, data lines RLINE and WLINE connected to each of the sense amplifiers 102 via the column switches 106 and 107, a first and second ports PORT 1 and 2 for inputting and outputting write data and read data, and an input/output circuit 230 for connecting the PORT 1 and 2 with the data lines RLINE and WLINE. The pseudo dual-port memory can be configured by using an ordinary DRAM array. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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