发明名称 |
Successive approximation ADC with binary error tolerance mechanism |
摘要 |
A successive approximation ADC is disclosed. A comparator receives and compares a sampled input signal and an output of a DAC. Non-binary successive approximation register (SAR) control logic controls sampling of the input signal and controls a sequence of comparisons based on comparison result of the comparator. The SAR control logic controls each comparison when signal or charge in the DAC has not been completely settled. A binary-error-tolerant corrector is then used to compensate the sampling error.
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申请公布号 |
US7724174(B2) |
申请公布日期 |
2010.05.25 |
申请号 |
US20080247199 |
申请日期 |
2008.10.07 |
申请人 |
HIMAS MEDIA SOLUTIONS, INC.;NCKU RESEARCH AND DEVELOPMENT FOUNDATION |
发明人 |
CHANG SOON-JYH;LIU CHUN-CHENG;HUANG CHIH-HAUR |
分类号 |
H03M1/34 |
主分类号 |
H03M1/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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