发明名称 LAYOUT DESIGN METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 A circuit and a method of layout-designing a circuit based on circuit information. The method includes generating layout information including a core region based on the circuit information, laying out an I/O circuit in a region other than the core region on the layout information based on the circuit information, determining a layout-permitted region of pads, which is included in regions other than the core region and a layout region of said I/O circuit, based on circuit information, and laying out the pads in the layout-permitted region.
申请公布号 US2010123252(A1) 申请公布日期 2010.05.20
申请号 US20090614833 申请日期 2009.11.09
申请人 FUJITSU MICROELECTRONICS LIMITED 发明人 USHIYAMA KENICHI
分类号 H01L23/52;G06F17/50 主分类号 H01L23/52
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