摘要 |
A data input circuit for a semiconductor memory apparatus includes a data latch block that, according to a data strobe signal, latches data and outputs the latched data; a data output controlling unit that determines a phase difference between the data strobe signal and a clock signal, and activates a data output control signal; and a data delay block that, when the data output control signal is activated, delays the data output from the data latch block for a predetermined time, and outputs the delayed data.
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