DELAY SIMULATION DEVICE, DELAY SIMULATION METHOD, PLD MAPPING DEVICE, PLD MAPPING METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

Provided is a delay simulation device comprised of an input means (4) for inputting information including a netlist, library, and load capacity, and simulation means (2). In the library, a plurality of distortion patterns of the input waveforms of a cell is defined for the logic states of the cell, and the delay values corresponding to the distortion pattern of the input waveform, the slope of the input waveform, and the load capacity are defined. The simulation means (2) selects the distortion pattern of the input waveform corresponding to the logic state of the cell, determines the slope of the input waveform based on the load capacity, and calculates the delay time so that delay values corresponding to the distortion pattern of the input waveform, the slope of the input waveform, and the load capacity are acquired from the library.