VERTICAL JUNCTION FIELD EFFECT TRANSISTORS HAVING SLOPED SIDEWALLS AND METHODS OF MAKING
摘要
Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of < 5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.
申请公布号
WO2010054073(A2)
申请公布日期
2010.05.14
申请号
WO2009US63391
申请日期
2009.11.05
申请人
SEMISOUTH LABORATORIES, INC.;SHERIDAN, DAVID, C.;RITENOUR, ANDREW, P.