CLOCK DIVISION CIRCUIT, CLOCK DISTRIBUTION CIRCUIT, CLOCK DIVISION METHOD, AND CLOCK DISTRIBUTION METHOD

摘要

Provided is a clock division circuit which generates a clock signal enabling execution or a correct communication expected in the communication with a circuit operating at a different frequency clock.  The clock division circuits (10a, b) reduce S clock pulses in the input clock signal by S - N clock pulses in accordance with the division ratio defined by the N/S so as to generate an output clock signal obtained by N/S-dividing the input clock signal.  The clock division circuits (10a, b) generates a control signal which reduces with a higher priority, the clock pulses other  than those at the communication timing of the data communication performed by a target circuit using the output clock signal among the S clock pulses of the input clock signal.  Furthermore, the clock pulses of the input clock signal are reduced in accordance with the generated control signal, thereby generating an output clock signal.