发明名称 Video processing circuit and method of video processing
摘要 Video stream processing, such as processing that includes MPEG decoding an subsequent post-processing involves using signal processing circuitry (102, 106) to execute a first and a second video stream processing function. The first video stream processing function produces frame data of successive video frames in a temporally ordered output sequence of frames. The second video stream processing function uses the frame data in an ordered input sequence of frames that differs from the output sequence, for example because later P-frames are needed to decode B frames. The frame data is buffered between application of the first and second video processing function to the frame data. A first and a second. buffer memory (12, 106) are used. The first buffer memory (12) is coupled to the signal processing circuitry via a shareable channel (15) such as an external IC terminals, but the processing circuitry does not use the shareable channel (15) to access the second buffer memory (106). The second video processing function reads frame data from first and second ones of the frames selectively from the first and second buffer memory (12, 106) respectively. The second ones of the frames occur in the same temporal order in both the input and output sequence. The first ones of the frames contain at least all particular frames whose position relative to the second ones of the frames in the output sequence differs from the position of the particular frames relative to the second ones of the frames in the input sequence.
申请公布号 US7706377(B2) 申请公布日期 2010.04.27
申请号 US20050591390 申请日期 2005.02.25
申请人 NXP B.V. 发明人 VAN DER WOLF PIETER;RIEMENS ABRAHAM KAREL;GANGWAL OM PRAKASH
分类号 H04L12/28;H04N7/26;H04N7/50 主分类号 H04L12/28
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