发明名称 Reading circuitry in memory
摘要 A reading circuit in a memory having a first memory cell coupled to a first bit line and a second bit line and a second memory cell coupled to the second bit line and a third bit line, is provided. The reading circuitry comprises a source side sensing circuit, a drain side bias circuit, a first selection circuit and a second selection circuit. The drain side bias circuit provides a drain side bias. The first selection circuit connects the second bit line and the third bit line to the drain side bias circuit in a read operation mode. The second selection circuit connects the first bit line to the source side sensing circuit so that a source current of the first memory cell is sensed.
申请公布号 US7706185(B2) 申请公布日期 2010.04.27
申请号 US20070783334 申请日期 2007.04.09
申请人 MACRONIX INTERNATIONAL CO., LTD. 发明人 CHEN CHUNG-KUANG
分类号 G11C11/34 主分类号 G11C11/34
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