| 摘要 |
PURPOSE: A multi-execution processing unit with instruction blocking sequencer logic is provided to use sequencer logic which responds to sequence instructions in an instruction stream, thereby enabling other execution units to issue and execute other instructions during the sequencer logic issues multiple instructions which are related to operations with long waiting time. CONSTITUTION: An instruction buffer logic(228) provides instructions to the first and the second operation units(202,204). A multi-thread issuance logic(206) is combined with the instruction buffer logic, a first operation unit, and a second operation unit. A multi-thread issuance logic includes a first and a second issuance selection logics(222) which output instructions from multiple threads to the first and the second operation unit. A first and a second multiplexers includes an output unit which communicates with the first issuance selection unit, a first input unit, and a second input unit. The first input unit receives instructions from the instruction buffer logic. A sequencer(236) is combined with the second input unit of the first and second multiplexers.
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