| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To solve the problem that it is not possible to flexibly select a hardware thread while securing the minimum execution time of the hardware thread in a conventional multi-thread processor. <P>SOLUTION: A multi-thread processor includes: a plurality of hardware threads each of which generates an independent instruction flow; a first thread scheduler 19 that outputs a first thread selection signal TSEL designating a hardware thread to be executed in the next execution cycle; a first selector that outputs an instruction generated by the selected hardware thread according to the first thread selection signal TSEL; and an arithmetic circuit that executes an instruction output from the first selector, wherein whenever a hardware thread is executed in the arithmetic circuit, the first thread scheduler 19 updates the priority rank of the executed hardware thread and outputs the first thread selection signal TSEL in accordance with the updated priority rank. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
