发明名称 Digital loop filter for all-digital phase-locked loop design
摘要 A digital loop filter installed in an all-digital phase-locked loop (PLL) receives a digitally controlled oscillator (DCO) control code transmitted from a PLL controller in the all-digital PLL, and calculate an average value, such that the PLL controller can produce another DCO control code by the average value for controlling and adjusting an output signal of a digitally controlled oscillator (DCO) in the neighborhood of the average value to maintain compensating a phase/frequency difference with an input signal, so as to minimize the jitter effect of the input signal on the all-digital PLL, reduce the jitter effect of the output signal, and keep tracking and locking the frequency and the phase of the input signal.
申请公布号 US7696832(B1) 申请公布日期 2010.04.13
申请号 US20080256316 申请日期 2008.10.22
申请人 NATIONAL CHIAO TUNG UNIVERSITY 发明人 LEE CHEN-YI;CHUNG CHING-CHE
分类号 H03L7/06;H03L7/08;H03L7/085 主分类号 H03L7/06
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