发明名称 |
Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to N wells and P wells |
摘要 |
A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address is not assigned while the memory cell is power-supplied through the well tap.
|
申请公布号 |
US7692943(B2) |
申请公布日期 |
2010.04.06 |
申请号 |
US20070000135 |
申请日期 |
2007.12.10 |
申请人 |
RENESAS TECHNOLOGY CORP.;HITACHI ULSI SYSTEMS CO., LTD. |
发明人 |
OSADA KENICHI;KAWAHARA TAKAYUKI;YAMAGUCHI KEN;SAITO YOSHIKAZU;KITAI NAOKI |
分类号 |
G11C5/02;G11C11/413;G06F11/10;G11C7/22;G11C7/24;G11C29/00;G11C29/42;H01L21/8244;H01L27/10;H01L27/11 |
主分类号 |
G11C5/02 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|