发明名称 Chip package structure
摘要 A method of fabricating a chip package structure includes the steps of providing a lead frame having a die pad, plural leads and at least one structure enhancement element. A chip is then disposed on the die pad and plural bonding wires are formed to electrically connect the chip to the leads. Then, an upper encapsulant and a first lower encapsulant are formed on an upper surface and a lower surface of the lead frame, respectively. The first lower encapsulant has plural concaves to expose the structure enhancement element. Finally, the structure enhancement element is etched with use of the first lower encapsulant as an etching mask until the die pad and one of the leads connected by the structure enhancement element, or two of the adjacent leads connected thereby are electrically insulated.
申请公布号 US7683462(B2) 申请公布日期 2010.03.23
申请号 US20070734250 申请日期 2007.04.11
申请人 CHIPMOS TECHNOLOGIES (BERMUDA) LTD. 发明人 CHIOU JIE-HUNG;QIAO YONG-CHAO;WU YAN-YI
分类号 H01L23/495 主分类号 H01L23/495
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