| 摘要 |
Apparatus, methods and techniques for adjusting the phase offset used in sampling rate conversion uses a Farrow structure or the like to compensate for clock problems such as“clock jitter”and/or“clock drift”effects, which typically arise where one clock is truly independent of the other. A phase offset adjustment valueΔμbased on the measured data flow between clock domains across a transition interface and/or through a buffer is calculated. Where an output FIFO buffer is used, the measured data flow value represents the number of data words written to and read from the FIFO buffer, such as the current number of data words stored in the FIFO buffer or a counter value representing the net number of data words written to the FIFO buffer. The measured data flow value is compared to a target data flow value, which may be a range of values. The phase offset adjustment value may be updated and/or recalculated continuously and/or periodically and is added to or subtracted from the phase offsetμas necessary. Such systems are useful in software defined radio and the like and may be implemented on a variety of devices, including PLDs.
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