Chip-level underfill process and structures

摘要

A process comprises forming a first electrical interconnect structure on a surface of a singulated semiconductor chip having an alignment pattern. The alignment pattern is scanned and stored in a scanning device prior to application of a curable underfill coating to the surface of the singulated semiconductor chip. This is followed by applying a curable underfill coating (240) to the surface of the singulated semiconductor chip (200A) to produce a coated semiconductor chip. The process also includes a step of delivering the scanned and stored alignment pattern to an alignment and joining device positioned adjacent to and operatively associated with a substrate (250) having a second electrical interconnect structure alignable to make electrical contact with the first electrical interconnect structure. The coated semiconductor chip is placed in the alignment and joining device so that when the scanned and stored alignment pattern is activated the alignment and joining device positions the coated semiconductor chip so that the first electrical interconnect structure is aligned to make electrical contact with the second electrical interconnect structure. This is followed by activating the alignment and joining device to join the coated semiconductor chip to the substrate so that the first electrical interconnect structure is in electrical contact with the second electrical interconnect structure. In one embodiment, the first electrical interconnect structure is placed on a surface of a semiconductor chip array in a wafer to produce the electrically connectable semiconductor structure which is followed by dicing to produce at least one of the singulated semiconductor chips. Another embodiment comprises aligning the first and second electrical interconnect structures prior to applying the curable underfill coating.