| 摘要 |
<p>The objectives are to reduce the launch transition and eventually the risk of yield loss even with few indefinite value (don't care) bits within the input bits, such as in the case of test compression, without affecting the amount of test data, the failure detection rate, performance, or circuit design even with real speed scan testing while observing the internal signal lines, as well as to enable reduced power consumption in testing. A converting device (1) is provided with a specific internal signal line extracting unit (3), a specific internal signal line differentiating unit (5), a specifying unit (7) that specifies indefinite input value bits and input logic bits in the input bits, and an assignment unit (9) that assigns a logical value 1 or a logical value 0 to indefinite value bits in the input bits containing the specified indefinite input value bits. The specifying unit (7) is provided with an indefinite input value bit specifying unit (11) and an input logic bit specifying unit (13).</p> |
