| 摘要 |
<P>PROBLEM TO BE SOLVED: To improve debugging efficiency of a processor. <P>SOLUTION: A debugging mechanism 233 stores OPCODEs of the past six cycles in a shift register 234, and a scanning part scans and reads the OPCODEs stored in the shift register 234. The debugging mechanism may be configured to input a REQUEST_VALID signal and to store the OPCODE in the shift register only when the value of the REQUEST_VALID signal is "1". For the processor having a plurality of arithmetic units, the debugging mechanism may be configured to store OPCODEs of a plurality of the arithmetic units. The debugging mechanism may also be configured to selectively store the OPCODE or RUPT_CODE. <P>COPYRIGHT: (C)2010,JPO&INPIT |
