发明名称 |
PARTIAL BLOCK ERASE ARCHITECTURE FOR FLASH MEMORY |
摘要 |
A method and system for increasing the lifespan of a flash memory device by selectively erasing sub-blocks of a memory block. Each physical memory block of the flash memory device is dividable into at least two logical sub-blocks, where each of the at least two logical sub-blocks is erasable. Therefore, only the data of the logical sub-block is erased and reprogrammed while unmodified data in the other logical sub-block avoids unnecessary program/erase cycles. The logical sub-blocks to be erased are dynamically configurable in size and location within the block. A wear leveling algorithm is used for distributing data throughout the physical and logical sub-blocks of the memory array to maximize the lifespan of the physical blocks during programming and data modification operations. |
申请公布号 |
KR20100015423(A) |
申请公布日期 |
2010.02.12 |
申请号 |
KR20097020969 |
申请日期 |
2008.03.04 |
申请人 |
MOSAID TECHNOLOGIES, INC. |
发明人 |
KIM JIN KI |
分类号 |
G11C16/16;G11C16/02;G11C16/08;G11C16/14 |
主分类号 |
G11C16/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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