发明名称 Alternate Signaling Mechanism Using Clock and Data
摘要 Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.
申请公布号 US2010031077(A1) 申请公布日期 2010.02.04
申请号 US20090511973 申请日期 2009.07.29
申请人 SWOBODA GARY L 发明人 SWOBODA GARY L.
分类号 G06F1/12 主分类号 G06F1/12
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