发明名称 |
LITHOGRAPHY SIMULATION DEVICE, LITHOGRAPHY SIMULATION PROGRAM, AND METHOD FOR DESIGNING AND MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME |
摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a lithography simulation device for deciding the quality of a circuit layout or a mask pattern created therefor from various aspects, and to provide a lithography simulation program and a method for designing and manufacturing a semiconductor device using the device. <P>SOLUTION: A variation calculation section 44 outputs a variation on the basis of a variation model function. The variation is an index showing the size and deviation in a statistic distribution of a status values such as an edge position. An existence probability generating section 40 outputs Contour showing a finished pattern shape on a wafer on the basis of the simulation result. The existence probability generating section 40 outputs a distribution function that represents a variation degree of the finished pattern shape on the basis of the simulation result stored in a simulation result storing section 46. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
申请公布号 |
JP2010026076(A) |
申请公布日期 |
2010.02.04 |
申请号 |
JP20080184994 |
申请日期 |
2008.07.16 |
申请人 |
RENESAS TECHNOLOGY CORP |
发明人 |
TAOKA HIRONOBU |
分类号 |
G03F1/36;G03F1/68;G03F1/70 |
主分类号 |
G03F1/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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