发明名称 |
DIGITAL DELAY LINE AND APPLICATION THEREOF |
摘要 |
A digital delay line includes a plurality of hysteresis-based delay cells electrically connected in series. These hystersis delay units in the hysteresis-based delay cells may be similar or different. All of the hysteresis delay units respectively have an inverter mode and a hesteresis mode. The delay and resolution of the hysteresis delay unit may be derived from the time difference in the inverter mode and hysteresis mode. Such a digital delay line applied to a digital phase locked loop may reduce consumption of area and power.
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申请公布号 |
US2010013533(A1) |
申请公布日期 |
2010.01.21 |
申请号 |
US20090390776 |
申请日期 |
2009.02.23 |
申请人 |
LEE CHEN-YI;YU JUI-YUAN;CHEN JUINN-TING |
发明人 |
LEE CHEN-YI;YU JUI-YUAN;CHEN JUINN-TING |
分类号 |
H03L7/06;H03H11/26 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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