| 摘要 |
A cache memory device includes an address generation unit, a data memory, a tag memory, and a hit judging unit. The address generation unit generates a prefetch index address included in a prefetch address based on an input address supplied from a higher-level device. The tag memory stores a plurality of tag addresses corresponding to a plurality of line data stored in the data memory. Further, the tag memory comprises a memory component that is configured to receive the prefetch index address and an input index address included in the input address in parallel and to output a first tag address in accordance with the input index address and a second tag address in accordance with the prefetch index address in parallel. The hit judging unit performs cache hit judgment of the input address and the prefetch address based on the first tag address and the second tag address.
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