发明名称 MICROPROCESSOR ARRANGEMENT HAVING AN ENCODING FUNCTION
摘要 <p>A microprocessor configuration includes a data bus for data transfer between functional units. On the bus side, each unit contains an encryption/decryption unit that is controlled synchronously by a random number generator. The configuration permits a relatively high level of security against monitoring of the data transferred via the data bus, with a feasible level of additional circuit complexity.</p>
申请公布号 EP1234239(B1) 申请公布日期 2010.01.06
申请号 EP20000983200 申请日期 2000.11.30
申请人 INFINEON TECHNOLOGIES AG 发明人 GAMMEL, BERNDT;KNIFFLER, OLIVER;SEDLAK, HOLGER
分类号 G06F12/14;G06F1/00;G06F15/00;G06F21/12;G06F21/60;G06F21/85;G09C1/00;H04L9/20 主分类号 G06F12/14
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