| 摘要 |
<P>PROBLEM TO BE SOLVED: To precise evaluate long-term jitters, and to prevent malfunctions of a circuit, in advance. Ž<P>SOLUTION: A first oscillator 10 generates a reference clock CKref. A PLL circuit 14 generates an output clock CKout, on the basis of the reference clock CKref from the first oscillator 10. An abnormal oscillation monitoring part 20 receives the reference clock CKref, by branching it, and generates a reference timing signal S1 to be asserted, after a lapse of prescribed time of integer multiples of a period of the reference clock CKref. The abnormal oscillation monitoring part 20 asserts an abnormality detection signal S2, when timing of an edge of the output clock CKout deviates from a prescribed range to be specified, according to an edge of the reference timing signal S1. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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