| 摘要 |
PROBLEM TO BE SOLVED: To provide a technology for easily reproducing the behavior of currents when an ESD (electrostatic discharge) serge is applied in verifying whether or not wiring width or the number of vias is sufficient for currents running when the ESD server is applied. SOLUTION: The layout verification device includes: a circuit diagram editor for generating change circuit diagram data 12 corresponding to a changed circuit diagram after a circuit diagram is changed from circuit diagram data 11 corresponding to the circuit diagram of a semiconductor integrated circuit; a circuit simulator for performing circuit simulation to the changed circuit diagram data 12; and a verification tool (layout/circuit diagram collation tool, resistance network extraction tool, and wiring/via verification tool) for verifying the validity of the wiring width of the wiring of the semiconductor integrated circuit and/or the number of vias from the layout data showing the result of the circuit simulation and the layout pattern of the semiconductor integrated circuit. COPYRIGHT: (C)2010,JPO&INPIT
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