| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem that a conventional frequency abnormality detecting circuit, in which a monitoring clock uses a frequency higher than that of a clock to be monitored, is expensive, requires a countermeasure against noise, and is difficult to mount on a substrate, and also, a conventional frequency abnormality detecting circuit, in which the monitoring clock uses a frequency lower than that of a clock to be monitored, is not only unable to detect an abnormality depending on timing of clock fixing but requires a separate configuration that prevents a warning from being issued since all register outputs constituting a shift register become "0" during a reset. SOLUTION: An upper-limit abnormality of a clock frequency is detected by comparing the magnitude of a count value of the number of clocks to be monitored with that of an upper-limit value. A lower-limit abnormality is detected by an output of a logical AND of a positive pulse outputted at a rising edge of synchronized monitoring clocks, an initial edge hold circuit output that outputs "High" by the pulse output, and a comparator output that compares the magnitude of a lower-limit value and that of the count value of the number of clocks to be monitored. COPYRIGHT: (C)2010,JPO&INPIT
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