| 摘要 |
A memory system according to an embodiment of the present invention comprises a DRAM 11, a NAND memory 12, a controller 134 having a control register 150 that specifies parallel-operating element specifying information indicating parallel operating elements 120A to 120D in the NAND memory 12 to be used at the time of data access and an address of data with respect to a NAND interface 140, the NAND interface 140 connected in parallel to the respective parallel operating elements 120A to 120D, and a CPU 131 that sets the parallel-operating element specifying information in the control register 150 according to the type of data to be accessed. |
