发明名称 |
Semiconductor device test apparatus and method |
摘要 |
There is provided a semiconductor test apparatus which uses a test processor to apply a test signal to a DUT having a semiconductor device within it to determine whether the memory is acceptable or not on the basis of a response signal, and uses a repair analysis computing unit to analyze the result of the test to determine how to replace a defective cell of the memory with a spare line. The repair analysis computing unit includes a fail memory which stores test results and a general-purpose repair analysis part which analyzes the test results in accordance with an MRA program and inserts and executes a user function of a user analysis program between units of analysis processing.
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申请公布号 |
US7613960(B2) |
申请公布日期 |
2009.11.03 |
申请号 |
US20040588636 |
申请日期 |
2004.02.18 |
申请人 |
ADVANTEST CORPORATION |
发明人 |
OKAWA KAZUYOSHI;OGINO JUNKO;YOSHINAGA MASAYUKI;HONDA HAJIME |
分类号 |
G11C29/00;G01R31/28;G11C29/56 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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地址 |
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