发明名称 |
Semiconductor integrated circuit with delay test circuit, and method for testing semiconductor integrated circuit |
摘要 |
A semiconductor integrated circuit includes an input side flip-flop; a combinational circuit having an input connected with the input side flip-flop; an output side flip-flop connected with an output of the combinational circuit; and a delay test circuit. The delay test circuit generates output clock pulses by removing an optional one from equal to or more than 3 continuing clock pulses of an input clock signal, and supplies the output clock pulse to the input side flip-flop and the output side flip-flop.
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申请公布号 |
US7613971(B2) |
申请公布日期 |
2009.11.03 |
申请号 |
US20060348414 |
申请日期 |
2006.02.07 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
ASAKA TOSHIHARU |
分类号 |
G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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