Menetelmä ja järjestely päällystys-, tulostus- tai painomenetelmällä tuotetun sähköä johtavan komponentin jälkikäsittelemiseksi,申请号FI20090006116-传众专利搜索

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发明名称	Menetelmä ja järjestely päällystys-, tulostus- tai painomenetelmällä tuotetun sähköä johtavan komponentin jälkikäsittelemiseksi
摘要
申请公布号	FI20096116(A0)	申请公布日期	2009.10.29
申请号	FI20090006116	申请日期	2009.10.29
申请人	VALTION TEKNILLINEN TUTKIMUSKESKUS	发明人	HAST, JUKKA;PETAEJAE, JARNO;KOLOLUOMA, TERHO;KOUKO, JARMO;KIISKINEN, HARRI
分类号		主分类号
代理机构		代理人
主权项
地址

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