| 摘要 |
PROBLEM TO BE SOLVED: To provide a design method of a semiconductor integrated circuit provided with a scan test function not only satisfying a required specification when an AC spec of an arithmetic processing circuit is specified, but also capable of preventing degradation of a failure detection rate. SOLUTION: This design method of a semiconductor integrated circuit including a scan test circuit structured such that a scan chain is composed by connecting, in series to one another, a plurality of flip-flops arranged corresponding to each of a plurality of logic circuit blocks constituting the arithmetic processing circuit, and test output date output from the respective logic circuit blocks in response to test input data supplied from an input terminal of the scan chain are extracted from an output terminal of the scan chain. The design method includes steps of: setting the flip-flop of an input-side first stage connected to a logic input terminal of the arithmetic processing circuit in the first stage of the scan chain; setting a flip-flop of the last output stage connected to a logic output terminal of the arithmetic circuit in the last stage of the scan chain; and automatically generating other circuit configurations of the scan test circuit by using an automatic test patter generation tool. COPYRIGHT: (C)2010,JPO&INPIT |
