SIMULATION DEVICE, SIMULATION METHOD, AND PROGRAM

摘要

<P>PROBLEM TO BE SOLVED: To provide a simulation device for verifying a clock-synchronized logic circuit including an N cycle multi-cycle path by a simple method in the initial stage of circuit design. Ž<P>SOLUTION: The simulation device configured to simulate design data of a circuit (402) to be verified including a logic circuit which performs an operation of an N cycle multi-cycle path synchronously with a clock signal is provided with: a design data generation means for generating the design data of a multi-cycle verification circuit (414) for selectively supplying an unfixed signal instead of a signal of a multi-cycle place in the circuit to be verified; a logical simulation means for performing logical simulation excluding delay based on the design data of the circuit to be verified and the design data of the multi-cycle verification circuit; and a comparison means for comparing the signal of the circuit to be verified by the logical simulation with the signal of an expected value of the circuit to be verified. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž