发明名称 DIGITAL RADIO PROCESSOR ARCHITECTURE WITH REDUCED DCO MODULATION RANGE REQUIREMENT
摘要 A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from pi/2, pi/4, pi/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of pi/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.
申请公布号 US2009252269(A1) 申请公布日期 2009.10.08
申请号 US20080060886 申请日期 2008.04.02
申请人 GUNTURI SARMA S;TANGUDU JAWAHARLAL;RAMAKRISHNAN STHANUNATHAN;JANARDHANAN JAYAWARDAN;SAHU DEBAPRIYA;MUKHERJEE SUBHASHISH 发明人 GUNTURI SARMA S.;TANGUDU JAWAHARLAL;RAMAKRISHNAN STHANUNATHAN;JANARDHANAN JAYAWARDAN;SAHU DEBAPRIYA;MUKHERJEE SUBHASHISH
分类号 H04L7/00 主分类号 H04L7/00
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