INTEGRATED CIRCUIT WITH TEST ARRANGEMENT, INTEGRATED CIRCUIT ARRANGEMENT AND TEXT METHOD

摘要

An integrated circuit (100) is disclosed comprising a test arrangement (110, 450) for testing a signal path (150) comprising a capacitive load (152), said test arrangement being arranged to, in a test mode, implement a method in accordance with the present invention by transferring a charge stored in the test arrangement (110, 450) to the capacitive load (152), and by deriving a test result from a voltage formed across the capacitive load (152) by said transferred charge.