De-Interlever That Simultaneously Generates Multiple Reorder Indices

摘要

A de-interleaver involves logic that receives a seed and that simultaneously generates from the seed a plurality of reorder indices. The plurality of reorder indices is usable for de-interleaving an incoming stream of interleaved code bits. Each plurality of simultaneously generated reorder indices generated corresponds to a set of simultaneously received code bits in the incoming stream. The reorder indices are converted into physical addresses in parallel and these physical addresses are used to store the set of code bits into a memory. Code bits for multiple sub-packets of different sub-packet sizes are typically present in memory at the same time. The code bits are then read out of memory to form an outgoing stream of de-interleaved code bits. The de-interleaver has a pipelined architecture such that sets of code bits are written into the memory at the same rate that sets of code bits are received onto the de-interleaver.