| 摘要 |
A memory control apparatus, a memory control method and an information processing system are disclosed. Fetch response data retrieved from a main storage unit (14a) is received, while bypassing a storage unit (19), by a first port (18) in which the received fetch response data can be set. The fetch response data retrieved from the main storage unit (14a), if unable to be set in the first port (18), is set in a second port (20) through the storage unit (19). A send-out control unit (22) performs priority control operation to send out, in accordance with a predetermined priority, the fetch response data set in the first port (18) or the second port (20) to the processor (13). As a result, the latency is shortened from the time when the fetch response data arrives to the time when the fetch response data is sent out toward the processor in response to a fetch request from the processor.
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