发明名称 Circuit and Method for a Vdd Level Memory Sense Amplifier
摘要 A circuit and method for a sense amplifier for sensing the charge stored by a memory cell is disclosed. The memory cell is coupled to a bit line, a complementary bit line and a differential sense amplifier is coupled to the bit line and the complementary bit line. A control signal couples a reference voltage to the complementary bit line. A positive precharge voltage is applied to the bit line and complementary bit line prior to the sense amplifier being enabled. The memory cell outputs a voltage to the bit line responsive to a word line, and the sense amplifier senses the differential voltage between the bit line and the complementary bit line responsive to a sense enable signal. A voltage regulator for generating the reference voltage, preferably about 80% of a positive supply voltage, is disclosed. A method of sensing data stored by a memory cell is disclosed.
申请公布号 US2009231939(A1) 申请公布日期 2009.09.17
申请号 US20080046276 申请日期 2008.03.11
申请人 HSU KUOYUAN PETER;KIM YOUNG SUK;WANG BING;HUANG MING CHIEH 发明人 HSU KUOYUAN PETER;KIM YOUNG SUK;WANG BING;HUANG MING CHIEH
分类号 G11C7/08;G11C7/12 主分类号 G11C7/08
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