WAFER LEVEL CHIP SIZE PACKAGE FOR IC DEVICES USING DICING PROCESS AND METHOD FOR MANUFACTURING THE SAME

摘要

A wafer level chip scale package and a manufacturing method thereof are provided to reduce the number of packaging processes using a dicing process and a thin film deposition process. An integrated device(220) is formed on a substrate(210). An electrode pad(230) is electrically connected to the integrated device. The conductive layer electrically connects a bump formed in the electrode pad and substrate backside. The electrode pad is reclaimed inside an insulating layer formed in an area which is adjacent to a dicing line. A passivation layer is formed on a conductive layer lower part and substrate back side. A photosensitive layer(240) is formed on the electrode pad.