| 摘要 |
A mute circuit has a resistor net configured to include a plurality of resistors connected in cascade between two reference voltage terminals, the resistor net being capable of outputting one of divided voltages from between the adjacent resistors, a selecting circuit configured to control selection of the divided voltage outputted from the resistor net based on logic of a selecting signal, a signal propagation determining circuit configured to monitor a voltage level of the divided voltage selected by the selecting circuit using an alternating test signal, and determine whether a signal indicating the monitored result propagates or not at the same cycle as that of the test signal, a memory circuit configured to store data corresponding to an output signal of the signal propagation determining circuit in association with the selecting signal, a first switching circuit configured to switch whether a DC blocking capacitor is charged or not according to the divided voltage outputted from between specific resistors in the resistor net, a second switching circuit configured to switch whether different reference voltages or the same reference voltages is applied to the two reference voltage terminals, and a switch controlling circuit configured to shut off a charge path to the DC blocking capacitor until a result of determination by the signal propagation determining circuit is obtained, select the divided voltage by the selecting circuit based on the data stored in the memory circuit and charge the DC blocking capacitor by switching the first switching circuit after the result of determination by the signal propagation determining circuit has been obtained, and stop charging the DC blocking capacitor by switching the first switching circuit after the output signal of the signal propagation determining circuit becomes steady.
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