| 摘要 |
With the clock data restoration device 1, as a result of the processing of a loop which comprises the sampler section 10, detection section 20, timing determination section 30, and clock output section 40, the respective phases of the clock signal CKXA, clock signal CKXB, and clock signal CK are adjusted to match the phase of the input digital signal, the digital signal sampling time indicated by the clock signal CKXA is adjusted to match the peak time of the distribution of data transition times in a case where the value D (n-2) and value D(n-1) of the preceding two bits differ from one another, and the digital signal sampling time indicated by the clock signal CKXB is adjusted to match the peak time of the distribution of data transition times in a case where the value D (n-2) and value D(n-1) of the preceding two bits are equal to one another. |
