| 摘要 |
A NAND flash memory device with a burst read latency function is provided to improve read performance of a NAND flash memory device and a memory system including the same by shortening the cycle of a read enable signal. An interface block(240) outputs an internal clock signal by receiving an external read enable signal during a read operation. A buffer clock control circuit(260) operates in response to a data output enable signal and the internal clock signal. A buffer clock generation circuit(280,300) receives the internal clock signal, and generates first and second buffer clock signals according to the control of the buffer clock control circuit. A data output buffer circuit(340) sequentially outputs read data in response to one of the first and second buffer clock signals. The buffer clock control circuit controls the buffer clock generation circuit to generate the second buffer clock signal having a single pulse when the data output enable signal is enabled. The buffer clock control circuit controls the buffer clock generation circuit in order to generate the first buffer clock signal having a phase difference between with the internal clock signal after burst read latency time is elapsed from when the external read enable signal is inputted.
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