发明名称 MULTILAYER CAPACITOR, WIRING BOARD INCORPORATING MULTILAYER CAPACITOR, DECOUPLING CIRCUIT AND HIGH FREQUENCY CIRCUIT
摘要 PROBLEM TO BE SOLVED: To obtain a multilayer capacitor that suppresses equivalent series inductance to a minimum and achieves a large capacity. SOLUTION: The multilayer capacitor having first and second principal plane terminal electrodes 20, 21 formed on first and second principal planes 12, 13 of a body 18 is provided. First and second side terminal electrodes 22, 23 are formed on four sides 14 to 17. The body 18 is divided into a low ESL section 24 on the first principal plane 12 and a large capacity section 25 on the second principal plane 13. In the low ESL section 24, a first via hole conductor 28 that electrically connects first and second low ESL internal electrodes 26, 27 and the first low ESL internal electrode 26 with the first principal plane terminal electrode 20 and a second via hole conductor 29 that electrically connects the second low ESL internal electrode 27 with the second principal terminal electrode 21 are formed. In the large capacity section 25, a first lead-out electrode 32 that electrically connects first and second high capacity internal electrodes 30, 31 and the first large capacity internal electrode 30 with a first side terminal electrode 22 and a second lead-out electrode 33 that electrically connects the second large capacity internal electrode 31 with a second side terminal electrode 23 are formed. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009194397(A) 申请公布日期 2009.08.27
申请号 JP20090121622 申请日期 2009.05.20
申请人 MURATA MFG CO LTD;INTEL CORP 发明人 NAITO YASUYUKI;TANIGUCHI MASAAKI;KURODA YOICHI;HORI HARUO;FIGUEROA DAVID G;RODRIGUEZ JORGE P;WATTS NICHOLAS R;HOLMBERG NICHOLAS L;HIOKI TAKESHI
分类号 H01G4/30;H01G4/12;H01G4/232;H01G4/40;H01L23/12;H05K1/02;H05K1/18 主分类号 H01G4/30
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