| 摘要 |
A circuit for testing word lines of a semiconductor memory device, is provided which includes a first test signal generator configured to generate first test signals in response to test mode signals, a second test signal generator configured to generate a second test signal in response to the test mode signals and a word line test signal, a first address predecoder configured to output first address information signals having first address information in response to the second test signal and a first address signal, and a second address predecoder configured to output second address information signals having second address information in response to the first test signals and second address signals.
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