| 摘要 |
A processing circuit according to the present invention includes a plurality of logic circuits (designated as L11, . . . , and L44) formed by arranging in arrays and is configured to input an output from a logic circuit to the logic circuit located on the following row. Each of the plurality of logic circuits includes an operation circuit (ALU) configured to perform an operation on inputted data; and a selecting unit (MUX) configured to select and output any one of an operation output from the operation circuit or an operation output from the logic circuit located on the preceding row.
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