发明名称 WAFER LEVEL CHIP SCALE PACKAGE INCLUDING REDISTRIBUTION SUBSTRATE AND METHOD OF FABRICATING THE SAME
摘要 A wafer level chip package and a manufacturing method thereof are provide to simplify a process and to use a semiconductor chip without the change in a wire bonding package or a flip chip bonding package by performing a cutting process after performing a molding process and mounting the semiconductor chips on the rewiring substrate member. A wafer level chip size package(100a) includes a semiconductor chip(101), and a rewiring substrate(200). The semiconductor chip includes a plurality of pads(120) arranged in one side with a first pitch. A plurality of connection wirings(230) arranged with a second pitch larger than the first pitch are equipped in one side of the rewiring substrate. The rewiring substrate electrically connects the plurality of pads to the plurality of connection wirings to extend the pad pitch from the first pitch to the second pitch.
申请公布号 KR20090081597(A) 申请公布日期 2009.07.29
申请号 KR20080007554 申请日期 2008.01.24
申请人 FAIRCHILD KOREA SEMICONDUCTOR LTD. 发明人 PARK, MIN HYO;CHOI, SEUNG YONG
分类号 H01L23/12 主分类号 H01L23/12
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