ICHER

摘要

The present invention provides a new memory device for storage of boot code for microprocessors. The device includes a memory array (130), a first block, and decoders (118, 120). The first block is defined as rows of the memory array. The decoders decode a memory access request for the data. The memory access request may be either one of a top-down or bottom-up address protocol. In another embodiment, an integrated circuit memory includes: a memory array (130), a decoder, a control (136), and a logic gate (132). The decoders select a row of the memory array. The control outputs either a bottom-up or a top-down address protocol signal. The logic gate outputs a logical "Exclusive Or" of the control signal and a corresponding bit of the memory request, whereby a memory request in a bottom-up address protocol is converted to a memory address in a top-down address protocol.